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36-mbit (1m x 36/2m x 18) pipelined dcd sync sram cy7c1444av25 cy7c1445av25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05351 rev. *e revised june 22, 2006 features ? supports bus operation up to 250 mhz ? available speed grades are 250, 200 and 167 mhz ? registered inputs and outputs for pipelined operation ? optimal for performance (double-cycle deselect) ? depth expansion without wait state ? 2.5v core power supply ? 2.5v/1.8v i/o power supply ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? provide high-performance 3-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? cy7c1444av25, cy7c1445av25 available in jedec-standard lead-free 100-pin tqfp package, lead-free and non-lead-free 165-ball fbga package ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1444av25/cy7c1445av25 sram integrates 1m x 36/2m x 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth- expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be written. this device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.this feature allows depth expansion without penal- izing system performance. the cy7c1444av25/cy7c1445av25 operates from a +2.5v core power supply while all outputs operate with a +2.5v or 1.8v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 250 mhz 200 mhz 167 mhz unit maximum access time 2.6 3.2 3.4 ns maximum operating current 435 385 335 ma maximum cmos standby current 120 120 120 ma note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 2 of 26 1 2 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d, dqp d byte write register dq c ,dqp c byte write register dq b ,dqp b byte write register dq a, dqp a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a, dqp a byte write driver dq b ,dqp b byte write driver dq c ,dqp c byte write driver dq d, dqp d byte write driver input registers a 0,a1,a a[1:0] sleep control zz e 2 dqs dqp a dqp b dqp c dqp d logic block diagram ? cy7c1444av25 (1m x 36) address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b byte write register dq a , dqp a byte write register enable register oe sense amps memory array adsp 2 a [1:0] mode ce 2 ce 3 gw bwe pipelined enable dq s, dqp a dqp b output registers input registers e output buffers dq b , dqp b byte write driver dq a, dqp a byte write driver sleep control zz a 0, a1, a logic block diagram ? cy7c1445av25 (2m x 18)
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 3 of 26 pin configurations a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1444av25 (1m x 36) nc a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1445av25 (2m x 18) nc 100-pin tqfp pinout a a
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 4 of 26 pin configurations (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1444av25 (1m x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1445av25 (2m x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc a nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd ?v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 5 of 26 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1: a0 are fed to the two-bit counter. . bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all by tes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not connected for bga. where referenced, ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presente d to the device are captured in the address registers. a1: a0 are also l oaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sample d on the rising edge of clk, active low . when asserted low, addresses presente d to the device are captured in the address registers. a1: a0 are also l oaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by th e addresses presented during the previous clock rise of the read cycle . the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved bur st sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 6 of 26 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the cy7c1444av25/cy7c1445av25 supports secondary cache in systems utilizi ng either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement th rough the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address adv ancement logic and the address register while being presented to the memory core. the corre- sponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate thro ugh the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. after th e first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. the cy7c1444av25/cy7c1445av25 is a double-cycle deselect part. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tri-state immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at cl ock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during th is first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dq x inputs is written into the corre- sponding address location in the memory core. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1444av25/cy7c1445av25 provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write input will se lectively write to only the desired bytes. bytes not select ed during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1444av25/cy7c1445av25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will tri-state the output drivers. as a safety precaution, dq are automati- cally tri-stated whenever a writ e cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be disconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pi n can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pi n can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag-clock clock input to the jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die nc/72m,nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. nc/72m, nc/144m,nc/288m, nc/576m and nc/1g are address expansion pi ns are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 7 of 26 byte(s). adsc triggered write accesses require a single clock cycle to complete. the address pr esented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1444av25/cy7c1445av25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so will tri-state the output drivers. as a safety precaution, dq x are automati- cally tri-stated whenever a wr ite cycle is dete cted, regardless of the state of oe . burst sequences the cy7c1444av25/cy7c1445av25 provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifical ly to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. both read and write burst operations are supported. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low . interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 100 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current th is parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 8 of 26 truth table [2, 3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tri-state deselect cycle, power down none l l x l l x x x x l-h tri-state deselect cycle, power down none l x h l l x x x x l-h tri-state deselect cycle, power down none l l x l h l x x x l-h tri-state deselect cycle, power down none l x h l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes: 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only 2 chip selects ce 1 and ce 2 . 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cyc les. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low).
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 9 of 26 partial truth table for read/write [4, 8] function (cy7c1444av25) gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? (dq a and dqp a ) hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c ) hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d ) hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx truth table for read/write [4, 8] function (cy7c1445av25) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x note: 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 10 of 26 ieee 1149.1 serial boundary scan (jtag) the cy7c1444av25/cy7c1445av25 incorporates a serial boundary scan test access port (tap). this part is fully compliant with ieee standard 11 49.1. the tap operates using jedec-standard 2.5v/1.8v i/o logic level. the cy7c1444av25/cy7c1445av25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any regist er. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 11 of 26 when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr st ate. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit# 89 (for 165-fbga packages).when this scan cell, called the
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 12 of 26 ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [9, 10] symbol parameter min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 13 of 26 2.5v tap ac test conditions input pulse levels ................................................ v ss to 2.5v input rise and fall time........... .......................................... 1 ns input timing referenc e levels .........................................1.25v output reference levels.................................................1.25v test load termination supply vo ltage.............................1.25v 2.5v tap ac output load equivalent 1.8v tap ac test conditions input pulse levels.............. ........................0.2v to v ddq ? 0.2 input rise and fall time .....................................................1 ns input timing reference levels...... ..................................... 0.9v output reference levels ............. ..................................... 0.9v test load termination supply vo ltage .............................. 0.9v 1.8v tap ac output load equivalent note: 11. all voltages referenced to v ss (gnd). t do 1.25v 20p f z = 50 ? o 50 ? t do 0.9v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; v dd = 2.5v 0.125v unless otherwise noted) [11] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 2.5v 2.1 v v ddq = 1.8v 1.6 v v ol1 output low voltage i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ddq = 1.8v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 1.8v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current gnd < v in < v ddq ?5 5 a
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 14 of 26 identification register definitions instruction field cy7c1444av25 cy7c1445av25 description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use architecture/memory type(23:18) 000110 000110 defines memory type and architecture bus width/density(17:12) 100111 010111 defines width and density cypress jedec id code (11:1) 00000110100 000001101 00 allows unique identification of sram vendor id register presence indicator (0) 1 1 i ndicates the presence of an id register scan register sizes register name bit size (x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (165-ball fbga package) 89 89 identification codes instruction code description extest 000 captures i/o ring contents. th is instruction is 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 15 of 26 165-ball fbga boundary scan order [ 12,13] cy7c1444av25 (1m x 36), cy7c1445av25 (2m x 18) bit # ball id bit # ball id bit # ball id bit # ball id 1 n6 26 e11 51 a3 76 n1 2 n7 27 d11 52 a2 77 n2 3n10 28g10 53b2 78p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7r9 32c11 57c1 82r3 8p9 33a11 58d1 83p2 9p10 34b11 59e1 84r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12 h11 37 a9 62 d2 87 p6 13 n11 38 b9 63 e2 88 r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19 l10 44 b6 69 k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23 h10 48 a4 73 k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 notes: 12. balls which are nc (no connect) are pre-set low. 13. bit# 89 is pre-set high.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 16 of 26 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v supply voltage on v ddq relative to gnd ..... ?0.5v to + v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v + 5% 1.7v to v dd industrial ?40c to +85c electrical characteristics over the operating range [14, 15] dc electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage for 2.5v i/o 2.375 2.625 v for 1.8v i/o 1.7 1.9 v v oh output high voltage for 2.5v i/o, i oh = ?1.0 ma 2.0 v for 1.8v i/o, i oh = ?100 a1.6v v ol output low voltage for 2.5v i/o, i ol = 1.0 ma 0.4 v for 1.8v i/o, i ol = 100 a0.2v v ih input high voltage [14] for 2.5v i/o 1.7 v dd + 0.3v v for 1.8v i/o 1.26 v dd + 0.3v v v il input low voltage [14] for 2.5v i/o ?0.3 0.7 v for 1.8v i/o ?0.3 0.36 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 435 ma 5-ns cycle, 200 mhz 385 ma 6-ns cycle, 167 mhz 335 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc all speeds 185 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 120 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc all speeds 160 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 135 ma notes: 14. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 17 of 26 capacitance [16] parameter description test conditions 100 tqfp max. 165 fbga max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd/ v ddq = 2.5v 6.5 7 pf c clk clock input capacitance 3 7 pf c i/o input/output capacitance 5.5 6 pf thermal resistance [16] parameter description test conditions 100 tqfp package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 c/w jc thermal resistance (junction to case) 2.28 3.2 c/w ac test loads and waveforms note: 16. tested initially and after any design or proc ess change that may affect these parameters. output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load output r = 14k ? r = 14k ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 1.8v (c) 1.8v i/o test load v ddq -0.2 gnd 90% 10% 90% 10% 1 ns 1 ns
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 18 of 26 switching characteristics over the operating range [21, 22] parameter description ?250 ?200 ?167 unit min. max. min. max. min. max. t power v dd (typical) to the first access [17] 111 ms clock t cyc clock cycle time 4.0 5.0 6.0 ns t ch clock high 1.5 2.0 2.4 ns t cl clock low 1.5 2.0 2.4 ns output times t co data output valid after clk rise 2.6 3.2 3.4 ns t doh data output hold after clk rise 1.0 1.5 1.5 ns t clz clock to low-z [18, 19, 20] 1.0 1.3 1.5 ns t chz clock to high-z [18, 19, 20] 2.6 3.0 3.4 ns t oev oe low to output valid 2.6 3.0 3.4 ns t oelz oe low to output low-z [18, 19, 20] 000 ns t oehz oe high to output high-z [18, 19, 20] 2.6 3.0 3.4 ns set-up times t as address set-up before clk rise 1.2 1.4 1.5 ns t ads adsc , adsp set-up before cl k rise 1.2 1.4 1.5 ns t advs adv set-up before clk rise 1.2 1.4 1.5 ns t wes gw , bwe , bw x set-up before clk rise 1.2 1.4 1.5 ns t ds data input set-up before clk rise 1.2 1.4 1.5 ns t ces chip enable set-up before clk rise 1.2 1.4 1.5 ns hold times t ah address hold after clk rise 0.3 0.4 0.5 ns t adh adsp , adsc hold after clk rise 0.3 0.4 0.5 ns t advh adv hold after clk rise 0.3 0.4 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.3 0.4 0.5 ns t dh data input hold after clk rise 0.3 0.4 0.5 ns t ceh chip enable hold after clk rise 0.3 0.4 0.5 ns notes: 17. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 18. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 19. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 20. this parameter is sampled and not 100% tested. 21. timing reference level is 1.25v when v ddq = 2.5v and 0.9v when v ddq = 1.8v. 22. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 19 of 26 switching waveforms read cycle timing [23] note: 23. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe,bw data out (dq) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst don?t care undefined x clz t
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 20 of 26 write cycle timing [23, 24] note: 24. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined d(a1) high-z data in (d) data out (q)
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 21 of 26 read/write cycle timing [23, 25, 26] notes: 25. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 26. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 bwe, bw x a3 don?t care undefined
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 22 of 26 zz mode timing [27, 28] notes: 27. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 28. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 23 of 26 ordering information not all of the speed, package and temperature ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 167 cy7c1444av25-167axc 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1445av25-167axc cy7c1444av25-167bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-167bzc cy7c1444av25-167bzxc 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-167bzxc cy7c1444av25-167axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1445av25-167axi cy7c1444av25-167bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-167bzi cy7c1444av25-167bzxi 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-167bzxi 200 cy7c1444av25-200axc 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1445av25-200axc cy7c1444av25-200bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-200bzc CY7C1444AV25-200BZXC 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-200bzxc cy7c1444av25-200axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1445av25-200axi cy7c1444av25-200bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-200bzi cy7c1444av25-200bzxi 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-200bzxi 250 cy7c1444av25-250axc 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1445av25-250axc cy7c1444av25-250bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-250bzc cy7c1444av25-250bzxc 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-250bzxc cy7c1444av25-250axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1445av25-250axi cy7c1444av25-250bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1445av25-250bzi cy7c1444av25-250bzxi 51- 85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1445av25-250bzxi
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 24 of 26 package diagrams note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*b
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 25 of 26 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered tr ademarks of intel corporation. powerpc is a trademark of ibm corporation. all product and company names mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.4 mm) (51-85165) 51-85165-*a
cy7c1444av25 cy7c1445av25 document #: 38-05351 rev. *e page 26 of 26 document history page document title: cy7c1444av25/cy7c1445av25 36-mbit (1m x 36/2m x 18) pipelined dcd sync sram document number: 38-05351 rev. ecn no. issue date orig. of change description of change ** 124418 03/04/03 cgm new data sheet *a 254909 see ecn syt part number changed from previous revision. new and old part number differ by the letter ?a? modified functional block diagrams modified switching waveforms added boundary scan information added i dd , i x and i sb values in the dc electrical characteristics added t power specifications in switching characteristics table removed 119 pbga package edited ordering information typo for 165-ball fbga part and package name *b 303533 see ecn syt changed the test condition from v dd = min to v dd = max for v ol in the electrical characteristics table replaced ja and jc from tbd to respective thermal values for all packages on the thermal resistance table changed i dd from 450, 400 & 350 ma to 435, 38 5 & 335 ma for 250, 200 and 167 mhz respectively changed i sb1 from 190, 180 and 170 ma to 185 ma for 250, 200 and 167 mhz respectively changed i sb2 from 80 ma to 100 ma for all frequencies changed i sb3 from 180, 170 & 160 ma to 160 ma for 250, 200 and 167 mhz respectively changed i sb4 from 100 ma to 110 ma for all frequencies changed c in , c clk and c i/o from 5, 5 and 7 pf to 6.5, 3 and 5.5 pf respectively for tqfp package changed t co from 3.0 to 3.2 ns and t doh from 1.3 ns to 1.5 ns for 200 mhz speed bin added lead-free information for 100-pin tqfp and 165 fbga packages *c 331778 see ecn syt modified address expansion balls in the pinouts for 165 fbga package as per jedec standards and updated the pin definitions accordingly modified v ol, v oh test conditions changed c in , c clk and c i/o to 7, 7and 6 pf from 5, 5 and 7 pf for 165 fbga package added industrial temperature grade changed i sb2 and i sb4 from 100 and 110 ma to 120 and 135 ma respectively updated the ordering information by shadi ng and unshading mpns as per avail- ability *d 417509 see ecn rxu converted from preliminary to final changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed i x current value in mode from ?5 & 30 a to ?30 & 5 a respectively and also changed i x current value in zz from ?30 & 5 a to ?5 & 30 a respectively on page# 16 modified test condition from v ih < v dd to v ih < v dd modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table replaced package name column with package diagram in the ordering information table replaced package diagram of 51-85050 from *a to *b *e 473229 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table.

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